1. Field of the Invention
The present invention relates to an image sensor and an image capturing system.
2. Description of the Related Art
In recent years, an image sensor including a complicated analog circuit, digital circuit, and signal processing circuit has been developed by combining a CMOS logic manufacturing process with an image sensor manufacturing process. For example, there is known an image sensor in which a plurality of pixels are two-dimensionally arrayed in the row and column directions and which incorporates an analog/digital converter (A/D converter).
As an image sensor including an A/D converter, there is known an arrangement in which an A/D converter is provided on each pixel column (column parallel type A/D conversion). With this arrangement, it is possible to decrease the conversion rate of the A/D converter to a readout rate for one row, thereby reducing the operation speed of the A/D converter, as compared with a case in which an A/D converter is provided outside an image sensor. This can reduce the power consumption, and also readily increase the readout rate from the image sensor.
As such image sensor including column parallel type A/D converters, an image sensor is known, which converts a pixel value into a digital value by counting, when discharging or charging the output voltage of a pixel, a time until a reference voltage is reached (Japanese Patent Laid-Open No. 2005-348325).
This conventional technique will be described with reference to FIGS. 13 and 14. FIG. 13 is a circuit diagram showing an example of the circuit arrangement of an image sensor including column parallel type A/D converters. FIG. 14 is a timing chart showing a temporal change in output level of an integrator 1018 shown in FIG. 13.
Referring to FIG. 13, a pixel 1001 includes a photoelectric conversion element. A signal output from the pixel 1001 is connected to an output terminal 1008 of the integrator 1018 via a correlation double sampling (CDS) circuit 1002, a sample/hold (S/H) circuit 1003, a column amplifier 1004, and a switch 1016. A fixed voltage V_DE is applied from a terminal 1006 to the input terminal (−) of the integrator 1018 via a switch 1005, a resistance 1019, and a switch 1017. A reference voltage V_REF is applied from a terminal 1007 to the other input terminal (+) of the integrator 1018. Assume that the fixed voltage V_DE is lower than the reference voltage V_REF.
The integrator 1018 has a time constant based on the resistance 1019 and a capacitor 1020. A comparator 1009 compares the voltage of the output terminal 1008 with the reference voltage V_REF. A trigger output 1010 of the comparator 1009 controls the data load timing of a memory unit 1012 via a sequential circuit 1011. The count output of a common counter 1013 is connected to the input terminal of the memory unit 1012.
The operation of the image sensor shown in FIG. 13 will be described with reference to the timing chart shown in FIG. 14. The switch 1016 is turned on, and a signal voltage Vsig1 from the column amplifier 1004 is held in the output terminal 1008 of the integrator 1018 at a time t0. The switch 1016 is then turned off, and the switches 1005 and 1017 are turned on. Upon turning on the switch 1017, the common counter 1013 starts counting.
The fixed voltage V_DE lower than the reference voltage V_REF is applied to the resistance 1019 via the switches 1005 and 1017. As a result, the integrator 1018 starts discharge toward the fixed voltage V_DE as a discharge end voltage with a negative slope determined according to the time constant based on the resistance 1019 and capacitor 1020. The voltage of the output terminal 1008 of the integrator 1018 becomes lower than the reference voltage V_REF at a time t1, and the comparator 1009 generates the trigger output 1010. At this time, the memory unit 1012 is selected by the trigger output, and the value of the common counter 1013 is loaded into the memory unit 1012. Furthermore, the trigger output 1010 causes the sequential circuit 1011 to operate, and the switch 1017 is turned off, thereby terminating discharge. The output signal of the memory unit 1012 is connected to a common horizontal output line 1014. After one memory unit 1012 is selected, the output signal of the selected memory unit 1012 is digitally output to the outside via an amplifier 1015. There has been proposed a technique which enables switching of a dynamic range by changing a reference voltage to be applied to a column parallel type A/D converter according to the strength of a pixel signal (Japanese Patent Laid-Open No. 2001-346106).
In the above-described conventional techniques, however, it takes a longer time to reach the reference voltage as the initial signal voltage is higher, thereby prolonging the time required for A/D conversion. This will be described with reference to FIG. 14. If a signal voltage is Vsig1, the time required for A/D conversion is a time t1−t0, as indicated by a thick dotted line. If, however, a signal voltage is Vsig0 higher than Vsig1, the time required for A/D conversion is a time t2−t0, which is longer by t2−t1.
If, for example, there is a mode in which a readout operation is performed by adding pixel signals as a readout mode of the image sensor, a signal voltage in this mode is higher than that in a mode in which a readout operation is performed without adding pixel signals. In the mode in which a readout operation is performed by adding pixel signals, therefore, the time required for A/D conversion is longer than that in the normal readout mode in which no pixel signals are added.